Accelerating Timing Closure on High-Speed Interfaces with Allegro TimingVision Environment: A Cavium and Cadence Case Study

Cavium is a company based in San Jose, California that develops highly integrated semiconductor processors for intelligent networking, communications, storage, video, and security applications. The company has design teams in Massachusetts, India, Taiwan, and China. A principal PCB designer at Cavium, Bill Munroe, and a colleague on the Post-Silicon Validation team design evaluation boards used to confirm the correct operation and electrical characteristics of the company’s network processors. They work on multi-layer boards for high-speed SerDes designs, typically with layer counts similar to those found in system server boards, averaging 12,000 unrouted connections and 3,000 nets.

Cavium, a company that develops highly integrated semiconductor processors, was facing a significant challenge in their PCB design process. The manual process of board routing was time-consuming, especially as chips increasingly used standards-based high-speed interfaces, had increasingly sensitive signals, and had more complex electrical and layout implementation constraints. The company's Post-Silicon Validation team, responsible for designing evaluation boards to confirm the correct operation and electrical characteristics of the company’s network processors, was spending 8 to 12 weeks on routing critical high-speed signals by hand. This was without using additional human resources. As the volume of chips requiring evaluation boards grew, schedule pressures were increasing. The team needed to have their boards ready when the chip came back from the fab, and as the number of network processors offered by Cavium increased, so did the number of designs.

The solution to Cavium's challenge was found within their existing toolset. As a Cadence shop, the team implemented the Allegro TimingVision environment, available within the Allegro PCB Designer constraint-driven PCB design environment. This technology provided real-time, color-coded visual feedback on timing and phase information right on their design canvas. The embedded timing engine analyzed signal interdependencies to develop smart delay and phase targets. This dramatically sped up the routing process, reducing it from weeks to days. The team also used Allegro Constraint Manager for design constraint management and Allegro PCB Router for miscellaneous logic. The Allegro TimingVision environment transformed Cavium’s PCB design process, allowing for faster 'what-if' analysis with fewer layers for their boards for routing study designs using DDRx interfaces. The team also took advantage of some auto-interactive technologies while using the Allegro TimingVision environment, such as Auto-interactive Delay Tuning (AiDT) technology and Auto-interactive Breakout Technology (AiBT) with Auto-interactive Trunk Routing (AiTR).

• The implementation of the Allegro TimingVision environment has significantly transformed Cavium’s PCB design process. The real-time, color-coded visual feedback on timing and phase information right on their design canvas has eliminated the need to switch back and forth between their design canvas and Allegro Constraint Manager. The technology’s embedded timing engine analyzes signal interdependencies to develop smart delay and phase targets, allowing for a more efficient and accurate design process. The team can now handle a larger volume of board designs without having to spend all night in the office. The high-quality Allegro tools have enabled them to deliver high-quality work with greater efficiency than in the past. The team has also learned valuable lessons in the process, such as routing DDR4 signals spaced at 5X the line width for better noise/coupling immunity and ensuring that differential pairs are all matched before trying to match lengths for all signals in a byte lane.

• 4X faster timing closure, without compromise on quality
• Ability to take on increased volume of PCB designs with existing resources
• Faster 'what-if' analysis with fewer layers for boards for routing DDRx interfaces